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FAN4810
Power Factor Correction Controller
Features
* TriFault DetectTM for UL1950 compliance and enhanced safety * Slew rate enhanced transconductance error amplifier for ultra-fast PFC response * Low power: 200A startup current, 5.5mA operating current * Low total harmonic distortion, high PF * Average current, continuous boost leading edge PFC * Current fed gain modulator for improved noise immunity * Overvoltage and brown-out protection, UVLO, and soft start * Synchronized clock output
General Description
The FAN4810 is a controller for power factor corrected, switched mode power supplies. The FAN4810 includes circuits for the implementation of leading edge, average current, "boost" type power factor correction and results in a power supply that fully complies with IEC1000-3-2 specification. It also includes a TriFault DetectTM function to help ensure that no unsafe conditions will result from single component failure in the PFC. Gate-driver with 1A capability minimizes the need for external driver circuit. Low power requirements improve efficiency and reduce component costs. The PFC also includes peak current limiting, input voltage brownout protection and a overvoltage comparator shuts down the PFC section in the event of a sudden decrease in load. The clock-out signal can be used to synchronize down-stream PWM stages in order to reduce system noise.
Block Diagram
16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 7 OSCILLATOR R Q GAIN MODULATOR 3.6k VEA -
+
1 IEAO POWER FACTOR CORRECTOR 0.5V 3.6k
-
13 VCC OVP + 2.75V
-
TRI-FAULT
+ -
VCC 17V 7.5V REFERENCE S Q VREF 14
IEA
+ + -
-1V
+ -
R S
Q PFC OUT Q 12
PFC ILIMIT
8
DUTY CYCLE LIMIT
6
1.25V VCC 25A
+ -
CLKOUT S VFB 2.45V
- +
Q
VIN OK R Q
11
5 CLKSD 9 VREF
10
VCC
UVLO
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FAN4810
PRODUCT SPECIFICATION
Pin Configuration
FAN4810 (Pin Out)
IEAO 1 IAC 2 ISENSE 3 VRMS 4 CLKSD 5 NC 6 RAMP 1 7 NC 8 16 VEAO 15 VFB 14 VREF 13 VCC 12 PFC OUT 11 CLK OUT 10 GND 9 GND
TOP VIEW
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name IEAO IAC ISENSE VRMS CLKSD NC RAMP 1 NC GND GND CLK OUT PFC OUT VCC VREF VFB VEAO Ground Ground Clock signal synchronized to PFC frequency PFC driver output Positive supply Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output Oscillator timing node; timing set by RTCT Function Slew rate enhanced PFC transconductance error amplifier output PFC AC line reference input to Gain Modulator Current sense input to the PFC Gain Modulator PFC Gain Modulator RMS line voltage compensation input Turn on/off PWM clock without disturbing PFC out
2
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PRODUCT SPECIFICATION
FAN4810
Abolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter VCC ISENSE Voltage Voltage on Any Other Pin IREF IAC Input Current Peak PFC OUT Current, Source or Sink PFC OUT, CLK OUT Energy Per Cycle Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (JA) Plastic DIP Plastic SOIC -65 -5 GND - 0.3 Min. Max. 18 0.7 VCCZ + 0.3 10 10 1 1.5 150 150 260 80 105 Units V V V mA mA A J C C C C/W C/W
Operating Conditions
Min. Temperature Range 0 Max. 70 Units C
Electrical Characteristics
Unless otherwise specified, VCC = 15V, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio Current Error Amplifier Input Voltage Range Transconductance Input Offset Voltage Input Bias Current VNON INV = VINV, VEAO = 3.75V -1.5 50 0 100 4 -0.5 2 150 15 -1.0 V mV A 11V < VCC < 16.5V VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V -40 40 50 50 Note 2 6.0 VNON INV = VINV, VEAO = 3.75V Conditions Min. 0 30 2.43 65 2.5 -0.5 6.7 0.1 -140 140 60 60 0.4 Typ. Max. Units 5 90 2.57 -1.0 V V A V V A A dB dB Voltage Error Amplifier
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FAN4810
PRODUCT SPECIFICATION
Electrical Characteristics(Continued)
Unless otherwise specified, VCC = 15V, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio OVP Comparator Threshold Voltage Hysteresis Tri-Fault Detect Fault Detect HIGH Time to Fault Detect HIGH VFB = VFAULT DETECT LOW to VFB = OPEN. 470pF from VFB to GND 0.4 -0.9 120 2.65 2.75 2 2.85 4 V ms 2.65 175 2.75 250 2.85 325 V mV 11V < VCC < 16.5V VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V -40 40 60 60 Conditions Min. 6.0 Typ. 6.7 0.65 -104 160 70 75 1.0 Max. Units V V A A dB dB
Fault Detect LOW PFC ILIMIT Comparator Threshold Voltage (PFC ILIMIT VTH - Gain Modulator Output) Delay to Output GAIN Modulator Gain (Note 3) IAC = 100A, VRMS = VFB = 0V IAC = 50A, VRMS = 1.2V, VFB = 0V IAC = 50A, VRMS = 1.8V, VFB = 0V IAC = 100A, VRMS = 3.3V, VFB = 0V Bandwidth Output Voltage Oscillator Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage PFC Dead Time CT Discharge Current Reference Output Voltage Line Regulation Load Regulation TA = 25C, I(VREF) = 1mA 11V 0.5 -1.0 220 150
0.6 -1.1
V V mV
300 1.05 2.40 1.25 0.40
ns
0.60 1.8 0.85 0.20 0.60 71
0.80 2.0 1.0 0.30 10 0.75 76 1 2
MHz 0.9 81 V kHz % % 84 kHz V 650 ns mA V mV mV 7.5 7.6 25 20
68 2.5 350 3.5 7.4 5.5 7.5 10 10
4
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PRODUCT SPECIFICATION
FAN4810
Electrical Characteristics(Continued)
Unless otherwise specified, VCC = 15V, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Temperature Stability Total Variation Long Term Stability PFC Minimum Duty Cycle Maximum Duty Cycle Output Low Voltage VIEAO > 4.0V VIEAO < 1.2V IOUT = -20mA IOUT = -100mA IOUT = 10mA, VCC = 9V Output High Voltage Rise/Fall Time Clock Duty Cycle Supply Start-up Current Operating Current Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis VCC = 12V, CL = 0 14V, CL = 0 12.4 2.5 200 5.5 13 2.8 350 7 13.6 3.1 A mA V V 45 47 50 % IOUT = 20mA IOUT = 100mA CL = 1000pF VCC - 0.8V VCC - 2V 50 90 95 0.4 0.7 0.4 0.8 2.0 0.8 0 % % V V V V V ns Line, Load, Temp TJ = 125C, 1000 Hours 7.35 5 Conditions Min. Typ. 0.4 7.65 25 Max. Units % V mV
Notes 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. Includes all bias currents to other circuits connected to the VFB pin. 3. Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x [IAC (VEAO - 0.625)]-1; VEAOMAX=5V.
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FAN4810
PRODUCT SPECIFICATION
Typical Performance Characteristics
180 160 TRANSCONDUCTANCE ( ) 140 120 100 80 60 40 20 0 0 1 2 VFB (V) 3 4 5
Voltage Error Amplifier (VEA) Transconductance (gm)
180 160 TRANSCONDUCTANCE ( ) 140 120 100 80 60 40 20 0 -500 VARIABLE GAIN BLOCK CONSTANT (K)
480 420 360 300 240 180 120 60 0 0 IEA INPUT VOLTAGE (mV) 500
0
1
2
3
4
5
VRMS(V)
Current Error Amplifier (IEA) Transconductance (gm)
Gain Modulator Transfer Characteristic (K)
( I GAINMOD - 84A ) -1 K = ---------------------------------------------------- mV IAC x ( 5 - 0.625 )
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PRODUCT SPECIFICATION
FAN4810
Power Factor Correction
Power factor correction makes a nonlinear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current inphase with the line voltage. Such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC of the FAN4810 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. In order to prevent ripple, which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the FAN4810 PFC is of the current-averaging type, no slope compensation is required.
PFC Circuit Blocks
Gain Modulator
Figure 1 shows a block diagram of the FAN4810. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1. A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator's output is inversely proportional to VRMS2 (except at unusually low values of VRMS where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is called K, and is illustrated in the Typical Performance Characteristics. The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage.
2.
3.
The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is: I AC x VEAO ------- -- - I GAINMOD = -------2-- x 1V V RMS (1)
More exactly, the output current of the gain modulator is given by: I GAINMOD = K x ( VEAO - 0.625V ) x I AC where K is in units of V-1. Note that the output current of the gain modulator is limited to 500A.
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7
FAN4810
PRODUCT SPECIFICATION
Current Error Amplifier
TriFault DetectTM
The current error amplifier's output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the ID of the boost MOSFET(s) and one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator's output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin.
Cycle-By-Cycle Current Limiter
To improve power supply reliability, reduce system component count, and simplify compliance to UL 1950 safety standards, the FAN4810 includes TriFault Detect. This feature monitors VFB (Pin 15) for certain PFC fault conditions. In the case of a feedback path failure, the output of the PFC could go out of safe operating limits. With such a failure, VFB will go outside of its normal operating area. Should VFB go too low, too high, or open, TriFault Detect senses the error and terminates the PFC output drive. TriFault detect is an entirely internal circuit. It requires no external components to serve its protective function.
Overvoltage Protection
The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle.
The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.75V, the PFC output driver is shut down. The OVP comparator has 250mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.50V. The VFB should be set at a level where the active and passive external power components and the FAN4810 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop.
16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 7 GAIN MODULATOR 1.6k VEA -
+
1 IEAO 0.5V 1.6k IEA
+ + - - + -
TRI-FAULT 2.75V
OVP +
-
S -1V
+ -
Q
R S
Q PFC OUT Q 12
PFC ILIMIT
R OSCILLATOR
Q
Figure 1. PFC Block Diagram
8
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PRODUCT SPECIFICATION
FAN4810
Error Amplifier Compensation
The output of the PFC is typically loaded by a PWM converter to produce the low voltages and high currents required at the outputs of a SMPS. PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. There are two major concerns when compensating the voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier's open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the FAN4810's voltage error amplifier has a specially shaped non-linearity such that under steady-state operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, thetransconductance of the voltage error amplifier will
increase significantly, as shown in the Typical Performance Characteristics. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier,to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. There is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Typical Performance Characteristics. For more information on compensating the current and voltage control loops, see Application Note AN42045. Application Note 42030 also contains valuable information for the design of this class of PFC.
VREF
VBIAS
PFC OUTPUT VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 VEA -
+
RBIAS
16 IEAO 1
VCC
IEA +
+ - -
0.22F CERAMIC
FAN4810 GND
15V ZENER
GAIN MODULATOR
Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers
Figure 3. External Component Connections to VCC
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FAN4810
PRODUCT SPECIFICATION
Oscillator (RAMP 1)
The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: 1 f OSC = --------------------------------------------------t RAMP + t DEADTIME (2)
It is important that the start-up delay is long enough to allow the PFC time to generate sufficient output power for the PWM DC converter. The start-up delay should be at least 5ms. Solving for the minimum value of Cdly: 25A C dly = 5ms x -------------- = 100nF 1.25V
Generating VCC
(6a)
The dead time of the oscillator is derived from the following equation: t RAMP V REF - 1.25 = C T x R T x In ----------------------------V REF - 3.75 (3)
at VREF = 7.5V: t RAMP = C T x R T x 0.51 The dead time of the oscillator may be determined using: 2.5V t DEADTIME = ---------------- x C T = 450 x C T 5.5mA (4)
The dead time is so small (tRAMP >> tDEADTIME) that the operating frequency can typically be approximated by: f OSC 1 = --------------t RAMP (5)
The FAN4810 is a voltage-fed part. It requires an external 15V, 10% (or better) shunt voltage regulator, or some other VCC regulator, to regulate the voltage supplied to the part at 15V nominal. This allows low power dissipation while at the same time delivering 13V nominal gate drive at the PFC OUT output. If using a Zener diode for this function, it is important to limit the current through the Zener to avoid overheating or destroying it. This can be easily done with a single resistor in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor's value must be chosen to meet the operating current requirement of the FAN4810 itself (7mA, max.) plus the current required by the gate driver output and zener diode. EXAMPLE: With a VBIAS of 20V, a VCC of 15V and the FAN4810 driving a total gate charge of 38nC at 100kHz (e.g., 1 IRF840 MOSFET ), the gate driver current required is: I GATEDRIVE = 100kHz x 38nC = 3.8mA V BIAS - V CC R BIAS = --------------------------------I CC + I G + I Z 20V - 15V R BIAS = ------------------------------------------------------ = 316 7mA + 3.8mA + 5mA Choose RBIAS = 330. The FAN4810 should be locally bypassed with a 1.0F ceramic capacitor. In most applications, an electrolytic capacitor of between 47F and 220F is also required across the part, both for filtering and as part of the start-up bootstrap circuitry. (7) (8)
EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: f OSC 1 = 100kHz = --------------t RAMP
Solving for RT x CT yields 1.96 x 10-4. Selecting standard components values, CT = 390pF, and RT = 51.1k.
Clock Out (Pin 11)
Clock output is a rail to rail CMOS driver. The PMOS can pull up within 15 ohms of the rail and the NMOS can pull down to within 7 ohms of ground. The clock turns on when the CLKSD pin is greater than 1.25V and the PFC output voltage is at rated operation value. The clock signal can be used to synchronize and provide on/ off control for downstream DC to DC PWM converters.
CLKSD (Pin 5)
Typical Applications
Figure 4 is the application circuit for a complete 125W power factor corrected power supply, designed using the methods and general topology detailed in Application Note 42046.
A current source of 25A supplies the charging current for a capacitor connected to this pin. Start-up delay can be programmed by the following equation: 25A C dly = t DELAY x -------------1.25V (6)
where Cdly is the required soft start capacitance, and tDELAY is the desired start-up delay.
10 REV. 1.0.12 9/24/03
PRODUCT SPECIFICATION
FAN4810
IN5406 KBLD6
L
F1 3.15A
3.1mH
15L9R482
D1
D2
~
C1 .68F
+
L1 Q1 IRF840
+385 V
AC INPUT 85 TO 260 V
N
BR1
R27 75K R2A
100F
C4 10nF
+
R7A
~
D12
C5
D9 MBR5140
(2) 453 K
R21 22
(2) 178 K
R1A
R7B
R2B R1B (2) 499 K
(2) IN5401 D13 R31 100 C3 100nF C2 470nF
R28 330
+
D3
L1
D6
C10F
C12
C19 1.0F C20 1.0F
RAMP1
75K 10K
R3
+
15V Zener
47F R4
C30
(not used) C7 71.5K R12 1.5nF C6 1 2 3 4 IEAO IAC ISENSE VRMS CLKSD VEAO FB REF VCC V01 16 15 14 13
C16 C15 C14 845K R11 41.2K
R6
CLK OUT
VCC
REF
ISENSE
(4) 1.2 R5D R5C R5B R5A
5 6 7 8
470pF C19 100nF C18 C26
12 11
CLK OUT RAMP1 GND
1nF
10nF
C13 100nF
1F
10
C31 2.37K R8
C9
C8 68nF
U1
GND 9
10nF
1nF
FAN4810
D8
Figure 4. 125W Power Factor Corrected Power Supply Using AN42046
1F
MBR5140
D10
MBR5140
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FAN4810
PRODUCT SPECIFICATION
Package Dimensions
16-Lead Plastic Dual Inline Package (PDIP) 0.300" Body Width
Symbol A A1 A2 B B1 C D D1 E E1 e eB L N Notes: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. D 8 1 Inches Min. Max. Millimeters Min. Max. Notes
-- .210 .015 -- .115 .195 .014 .022 .045 .070 .008 .014 .745 .840 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .160 16
-- 5.33 .38 -- 2.93 4.95 .36 .56 1.14 1.78 .20 .36 18.92 21.33 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 4.06 16
4 2
2
5
E1
D1
9
16
E e A A1 L B1 B eB A2 C
12
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PRODUCT SPECIFICATION
FAN4810
Package Dimensions (Continued)
16-Lead Small Outline IC (SOIC) 0.150"
Symbol A A1 B C D E e H h L N ccc Notes: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "C" dimension does not include solder finish thickness. 16 9 6. Symbol "N" is the maximum number of terminals. Inches Min. Max. Millimeters Min. Max. Notes
.053 .069 .004 .010 .013 .020 .0075 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0 -- 8 0.10 6.20 0.50 1.27
5 2 2
3 6
E
H
1
8
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C L h x 45 C e B
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FAN4810
PRODUCT SPECIFICATION
Ordering Information
Part Number FAN4810N FAN4810M FAN4810MX Temperature Range 0C to 70C 0C to 70C 0C to 70C Package 16-Pin MDIP (P16) 16-Pin Narrow SOIC (S16N) 16-Pin Narrow SOIC in Tape & Reel
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury of the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9/24/03 0.0m 001 Stock#DS30004800 2003 Fairchild Semiconductor Corporation

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